The present invention relates to integrated circuits, and more specifically relates to interconnect structures including airgaps and subtractively etched metal lines.
Generally, semiconductor devices include a plurality of circuits that form an integrated circuit fabricated on a single substrate, such as a silicon crystal substrate. A complex network of signal paths will normally be routed to connect the circuit elements distributed on the surface of the substrate. Efficient routing of these signals across the device typically requires the formation of multi-level or multi-layered interconnection schemes such as, for example, dual damascene wiring structures based on copper. Copper based interconnects are desirable due to their efficacy in providing high speed signal transmission between large numbers of transistors on a complex semiconductor chip. Within the interconnection structure, metal vias run perpendicular to the substrate and metal lines run parallel to the substrate. Further enhancement of the speed of signals and reduction of interaction of signals in adjacent copper lines (known as “cross-talk”) can be achieved in new IC product chips by surrounding the copper lines and vias in a low k or ultralow k dielectric, having a dielectric constant of about 1.5 to about 3.0. Still further speed enhancement can be achieved using an airgap structure because the dielectric constant of air is 1.0.